MIT PROCESSOR DB

Team Steering committee

FPGA

General Information

Manufacturer

SoC Name

Release Date

Process Node

nm

Logic Resources

Generation

Family/Subfamily

Model

CLBs

Slices per CLB

Slices

LUTs per CLB

Total LUTs

Flip-Flops per CLB

Total FFs

Memory & DSP

Distributed RAM

Block RAMs

uRAMs

DSP Multipliers

AI Engines

I/O & Interconnect

NoC Ports

I/O Banks

Max User I/Os

Max Differential Pairs

Clock Resources

Global Clock Buffers

Clock Regions

Buffers per Region

Regional Clock Buffers

External Interfaces

Max MGTs

Processing System

Ethernet MACs